The present invention relates to redundancy circuits for semiconductor memory and particularly to using dummy cells in redundancy circuits.
Semiconductor memory devices continue to increase in density. As the density of these devices increase, it is difficult to ensure that every cell within the semiconductor memory device is free of defects. In this way, after fabrication of the semiconductor memory device, the device is typically tested in order to determine whether defective cells exist within the memory device.
When defects are detected within some memory cells of the semiconductor memory device, it is typically not practical to discard the entire device. In order to enhance the yield of semiconductor memory devices, redundancy circuits, including redundancy word lines and redundancy cells, may be used in order to compensate for defective memory cells. In this way, where a defective memory cell is found, it may be replaced by a redundancy cell.
Redundancy circuits receive address information identifying the defective cell or word line, such that a redundant cell or word line may be used in its place. In such systems, the semiconductor memory device must be provided with sufficient redundancy cells and redundancy word lines in anticipation that some of the normal cells will be found to be defective after testing.
In order to provide adequate redundant memory cells and redundant word lines, a significant number of spare memory cell elements must be provided in case cell failure is detected. In cases where the number of spare cells significantly exceeds the number of defective cells, area deficiency is degraded.
Consequently, there exists a need for the present invention.